Saturday, December 7, 2013

Working With CACHE



                Cache Memory is considered a fastest memory, not totally because of its cell structure or type of semi-conductor used, its considered fast because the response time it quick when compared to all other memories.

             One thing you must know in-order to move further is, caching of a memory is decided my MMU, so MMU and Caches are always interlinked. MMU tables will decide which part of the memory is cacheable and which are not, and the caches contains the value at that corresponding address( or virtual address).

              Normally we do two operations on cache. Cache Flush and Cache Invalidate. For those all who are new to these concepts,

Cache Flush : Writing back values(present in cache) of the mapped address to its physical memory(ddr)

Cache Invalidation : Making mapped address invalid ( undo the mapping).


            As shown in the figure you can see caches have many levels, L1 , L2, L3 and each one may also be divided into Instruction cache and Data cache.

 Caches can give trouble in some situation , i will explain some situations :

1)  If some memory area is mapped to cache and processor is working on it, and in between you do a DMA transfer to the same address. Then the new data present in real memory(ram) will not be reflected in cache as no where processor was involved in DMA transfer. So processor still keeps on working with old data present in cache.

2) If we invalidate cache without flushing it, what happens is the new calculated data present in cache will not be written back to real memory, they mean while if processor tries to access that memory result may be unknown.